Periodic digital signals are commonly used in a variety of electronic devices, such as memory devices. Probably the most common of periodic digital signals are clock signals that are typically used to establish the timing of a digital signal or the timing at which an operation is performed on a digital signal. For example, data signals are typically coupled to and from memory devices, such as synchronous dynamic random access memory (“SDRAM”) devices, in synchronism with a clock or data strobe signal. Clock or data strobe signals are typically distributed to a number of circuits in the SDRAM devices through a “clock tree” and are used by the circuits to latch or capture the data signals.
As the speed of memory devices and other devices continue to increase, the “eye” or period in which a digital signal, such as a data signal, is valid becomes smaller and smaller, thus making the timing of a strobe signal or other clock signal used to capture the digital signal even more critical. In particular, as the size of the eye becomes smaller, the propagation delay of the strobe signal can be different from the propagation delay of the captured digital signal(s). As a result, the skew of the strobe signal relative to the digital signal can increase to the point where a transition of the strobe signal is no longer within the eye of the captured signal.
One technique that has been used to ensure the correct timing of a strobe signal relative to captured digital signals is to use a delay-lock loop (“DLL”), to generate the strobe signal. In particular, a delay-lock loop allows the timing of the strobe signal to be adjusted to minimize the phase error between the strobe signal and the valid eye of the digital signal. A typical delay-lock loop uses a delay line (not shown) consisting of a large number of delay stages. A reference clock signal is applied to the delay line, and it propagates through the delay line to the final delay stage, which outputs a delayed clock signal. The phase of the delayed clock signal is compared to the phase of the reference clock signal to generate a phase error signal. The phase error signal is used to adjust the delay provided by the delay stages in the delay line until the phase of the delayed clock signal is equal to the phase of the reference clock signal. The delayed clock signal is then coupled through a clock tree to circuits that will utilize the delayed clock signal.
As the operating speed of memory devices increases, the frequencies of clock signals needed to operate the memory devices at these higher speeds also increases. One difficulty encountered with these higher clock speeds is the difficulty in coupling high frequency clock signals through a clock tree or other signal path to circuits that are to use the clock signals. One approach that has been used to alleviate this problem is to divide the high frequency clock signal to generate a series of low frequency clock signals having multiple phases with transitions that coincide with the transitions of the high frequency clock signal. For example, with reference to FIG. 1, a high frequency clock signal CLK1 is divided into a lower frequency clock signal CLK2, and four phases of the CLK2 signal are generated, which are designated CLK2A, CLK2B, CLK2C and CLK2D. The CLK2D signal has the same phase as the CLK2 signal, the CLK2A signal has a phase of 90 degrees relative to the phase of the CLK2 signal, the CLK2B signal has a phase of 180 degrees relative to the phase of the CLK2 signal, and the CLK2C signal has a phase of 270 degrees relative to the phase of the CLK2 signal. Each of these clock signals CLK2A-D has a rising edge transition that coincides with a respective transition of the CLK1 signal. However, because the CLK2A-D signals have a frequency that is only half the frequency of the CLK1 signal, they can more easily be coupled through a clock tree or other signal path.
Another problem associated with the high operating speed of memory and other devices is excessive power consumption, particularly for portable electronic devices like notebook or other portable computers. Power is consumed each time a digital circuit is switched to change the logic level of a digital signal. The rate at which power is consumed by memory devices therefore increases with both the operating speed of such devices and the number of circuits being switched. Thus, the demands for ever increasing operating speeds and memory capacity are inconsistent with the demands for ever decreasing memory power consumption. A significant amount of power is consumed by delay-lock loops, which are commonly used in memory devices. Delay-lock loops consume a great deal of power because the delay lines used in such loops often contain a large number of delay stages, all of which are switched as a reference clock signal propagates through the delay line. The higher reference clock signal frequencies needed to operate the memory devices at higher speed causes these large number delay stages to be switched at a rapid rate, thereby consuming power at a rapid rate. A significant amount of power is also consumed in distributing clock signals generated by delay-lock loops throughout circuitry that use the clock signals for various purposes.
Attempts have been made to address the problems encountered with using higher clock signal frequencies. However, conventional approaches to solving these problems have been hindered by the wide range of operating speeds at which memory devices using delay-lock loops must be operable. A memory device may divide the frequency of a clock signal to produce a multi-phased clock signal having a lower frequency. However, it may be unnecessary to include circuitry in a memory device for performing these functions if the memory device will be installed in a system having a lower frequency clock signal. If, on the other hand, such circuitry is not included, the memory device may be inoperable when installed in a system having a higher frequency clock signal.
There is therefore a need for a method and system for allowing a memory or other electronic device to operate over a wide range of operating speeds, and may operate in a manner that minimizes power consumption.